Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits-Reference-Cited by-同舟云学术

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Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

Published:2001-04 Issue:2 Volume:9 Page:390-394
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Pant P.,Roy R.K.,Chattejee A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/19988/00924061.pdf?arnumber=924061

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Minimum Implant Area-Aware Placement and Threshold Voltage Refinement;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017-07

2. Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-10

3. Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-06

4. Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths;Proceedings of the 26th edition on Great Lakes Symposium on VLSI;2016-05-18

5. Variability-aware architecture level optimization techniques for robust nanoscale chip design;Computers & Electrical Engineering;2014-01

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