Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths
Author:
Affiliation:
1. Broadcom Limited, Bangalore, India
2. Broadcom Limited, Allentown, USA
3. Cochin University of Science & Technology, Kochi, India
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2902961.2902991
Reference8 articles.
1. S. Narendra and A. Chandrakasan "Leakage in nanometer CMOS technologies " Springer 2006. S. Narendra and A. Chandrakasan "Leakage in nanometer CMOS technologies " Springer 2006.
2. Cell library management for power optimization;Turner M. F.;Us patent -- US,2009
3. Design and optimization of dual-threshold circuits for low-voltage low-power applications
4. Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
5. Low power design using dual threshold voltage;Ho Y.;Proc. of the Conference on Asia South Pacific Design Automation,2004
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