A structured approach to post-silicon validation and debug using symbolic quick error detection

Author:

Lin David,Singh Eshan,Barrett Clark,Mitra Subhasish

Publisher

IEEE

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. How Good is Your Property? A New Metric for Formal Property Coverage;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

2. TIUP: Effective Processor Verification with Tautology-Induced Universal Properties;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

3. Customer centric hybrid recommendation system for E-Commerce applications by integrating hybrid sentiment analysis;Electronic Commerce Research;2022-10-29

4. RemembERR: Leveraging Microprocessor Errata for Design Testing and Validation;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10

5. A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays;IEEE Transactions on Emerging Topics in Computing;2022-04-01

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