A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays-Reference-Cited by-同舟云学术

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays

Author:

Sazeides Yiannakis¹^ORCID,Bramnik Arkady²,Gabor Ron³,Canal Ramon⁴^ORCID

Affiliation:

1. Department of Computer Science, University of Cyprus, Nicosia, Cyprus

2. Intel Development Center, M.T.M. Scientific Industries Center, Haifa, Israel

3. Toga Networks, Hod Hasharon, Israel

4. Department d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona, Spain

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computer Science Applications,Human-Computer Interaction,Information Systems,Computer Science (miscellaneous)

Link

Reference29 articles.

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2. Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures;2023 8th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM);2023-11-10