Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture

Author:

Zhang Fanchen,Hwong Daphne,Sun Yi,Garcia Allison,Alhelaly Soha,Shofner Geoff,Winemberg LeRoy,Dworak Jennifer

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Test Compaction Using (k, 1)-Cycle Tests;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

2. Dual Use Circuitry for Early Failure Warning and Test;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

3. X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

4. Functional Compaction for Functional Test Sequences;IEEE Access;2024

5. Storage-Based Logic Built-In Self-Test With Cyclic Tests;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-09

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