A Markov chain sequence generator for power macromodeling
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/8355/26328/01167565.pdf?arnumber=1167565
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Low Power Design with High-Level Power Estimation and Power-Aware Synthesis;2012
2. Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays;Journal of Low Power Electronics;2011-02-01
3. SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation;Journal of Low Power Electronics;2009-12-01
4. Functionally valid gate-level peak power estimation for processors;2009 10th International Symposium on Quality of Electronic Design;2009-03
5. A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits;21st International Conference on VLSI Design (VLSID 2008);2008
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