Author:
Jyh-Ming Wang ,Sung-Chuan Fang ,Wu-Shiung Feng
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
135 articles.
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1. Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
2. EXPLORING SUPPLY VOLTAGE AND TEMPERATURE VARIATION ON XOR-XNOR CELLS WITH CONVENTIONAL / NON-CONVENTIONAL TECHNIQUES;FACTA UNIV-SER ELECT;2024
3. Performance Analysis of Low Power Hybrid Full Adder Using Pass Transistor Logic;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14
4. Specific Design on Arithmetic Circuits with Low Power for VLSI Architectures;International Journal of Advanced Research in Science, Communication and Technology;2024-01-02
5. Full Swing Logic Based Full Adder for Low Power Applications;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024