Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra

Author:

Carsello Alex1,Feng Kathleen1,Kong Taeyoung1,Koul Kalhan1,Liu Qiaoyi1,Melchert Jackson1,Nyengele Gedeon1,Strange Maxwell1,Zhang Keyi1,Nayak Ankita1,Setter Jeff1,Thomas James1,Sreedhar Kavya1,Chen Po-Han1,Bhagdikar Nikhil1,Myers Zachary1,D'Agostino Brandon1,Joshi Pranil1,Richardson Stephen1,Bahr Rick1,Torng Christopher1,Horowitz Mark1,Raina Priyanka1

Affiliation:

1. Stanford University,CA,USA

Publisher

IEEE

Reference4 articles.

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. The Dataflow Abstract Machine Simulator Framework;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA;ACM Transactions on Reconfigurable Technology and Systems;2024-05-10

4. Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing;ACM Transactions on Computer Systems;2023-11-30

5. FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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