CMOS Compatible Process Integration of SOT-MRAM with Heavy-Metal Bi-Layer Bottom Electrode and 10ns Field-Free SOT Switching with STT Assist-Reference-Cited by-同舟云学术

CMOS Compatible Process Integration of SOT-MRAM with Heavy-Metal Bi-Layer Bottom Electrode and 10ns Field-Free SOT Switching with STT Assist

Published:2020-06 Issue: Volume: Page:
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Container-title:2020 IEEE Symposium on VLSI Technology
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Author:

Sato Noriyuki,Allen Gary A.,Benson William P.,Buford Benjamin,Chakraborty Atreyee,Christenson Michael,Gosavi Tanay A.,Heil Philip E.,Kabir Nafees A.,Krist Brian J.,O'Brien Kevin P.,Oguz Kaan,Patil Rohan R.,Pellegren James,Smith Angeline K.,Walker Emily S.,Hentges Patrick J.,Metz Matthew V.,Seth Mansi,Turkot Bob,Wiegand Christopher J.,Yoo Hui Jae,Young Ian A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9264988/9264985/09265028.pdf?arnumber=9265028

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4. Low‐Power and Field‐Free Perpendicular Magnetic Memory Driven by Topological Insulators;Advanced Materials;2023-06-25

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