An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS-Reference-Cited by-同舟云学术

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An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS

Published:2021-05 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)
language:
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Author:

Ko JongHyun,Park KwanWoo,Yong Suhyeong,Jeong TaeGam,Kim Tae Hak,Song Taigon

Funder

National R&D Program through the National Research Foundation of Korea(NRF)

Ministry of Science and ICT

National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT)

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9459630/9459631/09459665.pdf?arnumber=9459665

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology;Physica Scripta;2024-05-09

2. Design of Encoder based Half-Adder using GNRFET Technology in Ternary Logic;2023 International Conference on Next Generation Electronics (NEleX);2023-12-14

3. Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09

4. Comprehensive survey of ternary full adders: Statistics, corrections, and assessments;IET Circuits, Devices & Systems;2023-02-14

5. Looking Beyond 0 and 1: Principles and Technology of Multi‐Valued Logic Devices;Advanced Materials;2022-11-17

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