Real-time hardware implementation of HEVC video encoder for 1080p HD video

Author:

Miyazawa Kazuyuki,Sakate Hiroharu,Sekiguchi Shun-ichi,Motoyama Nobuaki,Sugito Yasuko,Iguchi Kazuhisa,Ichigaya Atsuro,Sakaida Shin-ichi

Publisher

IEEE

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Evaluation of Hardware-based Video Encoders on Modern GPUs for UHD Live-Streaming;2024 33rd International Conference on Computer Communications and Networks (ICCCN);2024-07-29

2. High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications;ACM Transactions on Design Automation of Electronic Systems;2022-03-08

3. ‘A Strong, Sustainable Legacy:’ The Environment and Japan’s Winter Olympics;The International Journal of the History of Sport;2021-08-12

4. Efficient Algorithm Adaptations and Fully Parallel Hardware Architecture of H.265/HEVC Intra Encoder;IEEE Transactions on Circuits and Systems for Video Technology;2019-11

5. Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN Cloud;2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC);2019-10

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