Vertical Inner Gate Transistors for 4F2 DRAM Cell
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9014608/08986540.pdf?arnumber=8986540
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part I: Defect-Based Statistical Compact Model;IEEE Transactions on Electron Devices;2024-08
2. Improved Parasitic Capacitance-Predictively Aware DTCO: Enhanced Cell Efficiency With Manufacturability and Scalability for 4F2 VCT-Based DRAM;IEEE Transactions on Electron Devices;2024-07
3. Retention Time Analysis in a 1T-DRAM With a Vertical Twin Gate and p+/i/n+ Silicon Nanowire;IEEE Transactions on Electron Devices;2022-09
4. Single-event transient characteristics of vertical gate-all-around junctionless field-effect transistor on bulk substrate;Applied Physics A;2021-01-07
5. Ferroelectric-Metal Field-Effect Transistor with Recessed Channel for 1T-DRAM Application;IEEE Journal of the Electron Devices Society;2021
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