A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity-Reference-Cited by-同舟云学术

A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity

Published:2024-02 Issue:2 Volume:71 Page:689-702
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wu Hao¹^ORCID,Chen Yong²^ORCID,Yuan Yiyang¹^ORCID,Yue Jinshan¹^ORCID,Fu Xiangqu¹^ORCID,Ren Qirui¹^ORCID,Luo Qing¹^ORCID,Mak Pui-In²^ORCID,Wang Xinghua³^ORCID,Zhang Feng¹^ORCID

Affiliation:

1. Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences (CAS), Beijing, China

2. State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macau, China

3. School of Information and Electronics, Beijing Institute of Technology, Beijing, China

Funder

Strategic Priority Research Program of the Chinese Academy of Sciences China

National Natural Science Foundation of China

Science and Technology Development Fund, Macau

Science and Technology Development Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10416295/10315715.pdf?arnumber=10315715

Reference24 articles.

1. RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging

2. In-Memory Computing: Advances and Prospects

3. 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

4. 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

5. A 28nm 15.59µJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes

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