A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity-Reference-Cited by-同舟云学术

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A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity

Published:2024 Issue: Volume: Page:1-15
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Wu Hao¹^ORCID,Chen Yong²^ORCID,Yuan Yiyang¹^ORCID,Yue Jinshan¹^ORCID,Wang Xinghua³^ORCID,Li Xiaoran³^ORCID,Zhang Feng¹^ORCID

Affiliation:

1. Institute of Microelectronics, Key Laboratory of Microelectronics Device and Integrated Technology, Chinese Academy of Sciences (CAS), Beijing, China

2. State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macau, China

3. School of Information and Electronics, Beijing Institute of Technology, Beijing, China

Funder

National Key Research Plan of China

Strategic Priority Research Program of the Chinese Academy of Sciences China

National Natural Science Foundation of China

Science and Technology Development Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/4/4359912/10562243.pdf?arnumber=10562243

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