Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS-Reference-Cited by-同舟云学术

Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS

Published:2024-07 Issue:7 Volume:71 Page:3157-3164
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wang Jinn-Shyan¹^ORCID,Chou Pei-Yuan²^ORCID

Affiliation:

1. Department of Electrical Engineering, and the SoC Research Center, Advanced Institute of Manufacturing with High-Tech Innovations, National Chung Cheng University, Chiayi, Taiwan

2. Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10575936/10477395.pdf?arnumber=10477395

Reference7 articles.

1. The Jitter Measurement Ways: The Instrumentation

2. Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator

3. A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler

4. CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

5. An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience

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