Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property
Author:
Affiliation:
1. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India
2. Department of Electrical Engineering, IIT Madras, Chennai, India
Funder
RF, Analog and Mixed Signal Laboratory, IIT Madras; and
Scientific and Engineering Research Board (SERB), Government of India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9841618/09783455.pdf?arnumber=9783455
Reference12 articles.
1. Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial
2. A 65-nm CMOS Continuous-Time Pipeline ADC Achieving 70-dB SNDR in 100-MHz Bandwidth
3. A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique
4. A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing
5. A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta–Sigma Modulator With VCO Quantizer Nonlinearity Cancellation
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2. Digital Reconstruction in Continuous-Time Pipelined Analog-to-Digital Converters;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
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