Hardware Acceleration of MUSIC Algorithm for Sparse Arrays and Uniform Linear Arrays

Author:

Li Zeying1ORCID,Wang Weijiang1ORCID,Jiang Rongkun1ORCID,Ren Shiwei1ORCID,Wang Xiaohua1,Xue Chengbo1ORCID

Affiliation:

1. School of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing, China

Funder

Chongqing Natural Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

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2. A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

3. An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA;2024 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS);2024-04-03

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