A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA
Author:
Affiliation:
1. School of Integrated Circuits and Electronics, Beijing Institute of Technology (BIT), Beijing, China
2. School of Information and Electronics, Beijing Institute of Technology (BIT), Beijing, China
Funder
Natural Science Foundation of Chongqing Municipality
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/92/10536717/10456566.pdf?arnumber=10456566
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