Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G
Author:
Affiliation:
1. Department of Electricity and Energy, Osmaneli Vocational School, Bilecik ¸Seyh Edebali University, Bilecik, Turkey
2. Department of Electronic Engineering, ETSI de Telecomunicación, Universidad Politécnica de Madrid, Madrid, Spain
Funder
MCIN/AEI/ 10
“ERDF A way of making Europe”
MCIN/AEI/10
“ESF Investing in your future”
Scientific and Technological Research Council of Turkey through the International Postdoctoral Fellowship Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10268488/10199159.pdf?arnumber=10199159
Reference33 articles.
1. A high-parallelism memory-based FFT processor with high SQNR and novel addressing scheme
2. Optimized Pipelined Fast Fourier Transform Using Split and Merge Parallel Processing Units for OFDM
3. A Mixed-Decimation MDF Architecture for Radix- $2^{k}$ Parallel FFT
4. A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems
5. A New Representation of FFT Algorithms Using Triangular Matrices
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3. Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
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