Robust Timing Error Detection for Multilevel Baud-Rate CDR
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH, USA
Funder
Intel Corporation Circuits SRS
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9904939/09839592.pdf?arnumber=9839592
Reference29 articles.
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4. A 1.24pJ/b 112Gb/s (870Gbps/mm) transceiver for in-package links in 7 nm FinFET;poon;Proc Symp VLSI Circuits,2021
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2. Complexity reduction in multilevel speculative DFEs with unconstrained receiver response;Microelectronics Journal;2023-08
3. Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery;IEEE Open Journal of Circuits and Systems;2023
4. A 12-Gbps, 0.24-pJ/b/dB PAM-4 Receiver With Dead-Zone Free SS-MMSE PD for CIS Link;IEEE Access;2023
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