Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability-Reference-Cited by-同舟云学术

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Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability

Published:2024-07 Issue:7 Volume:71 Page:3269-3281
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Mohamed Tarek¹^ORCID,van Santen Victor M.²^ORCID,Alrahis Lilas³^ORCID,Sinanoglu Ozgur³^ORCID,Amrouch Hussam¹^ORCID

Affiliation:

1. Semiconductor Test and Reliability (STAR), University of Stuttgart, Stuttgart, Germany

2. Chair of AI Processor Design, Technical University of Munich (TUM), Munich, Germany

3. Center for Cyber Security, New York University Abu Dhabi, Abu Dhabi, United Arab Emirates

Funder

Advantest through the Graduate School Intelligent Methods for Test and Reliability (GS-IMTR), University of Stuttgart

German Research Foundation (DFG) “ACCROSS: Approximate Computing aCROss the System Stack.”

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10575936/10535497.pdf?arnumber=10535497

Reference28 articles.

1. Statistical variability and reliability in nanoscale FinFETs

2. Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV

3. BSIM-CMG: A Compact Model for Multi-Gate Transistors

4. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

5. Sizing consideration for leakage control transistor

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