A 1.5-GS/s 6-bit Single-Channel Loop-Unrolled SAR ADC With Speculative CDAC Switching Control Technique in 28-nm CMOS

Author:

Lee Eunsang1ORCID,Pyo Changhyun1,Lee Sanghun1,Han Jaeduk1ORCID

Affiliation:

1. Department of Electronics Engineering, Hanyang University, Seoul, South Korea

Funder

Samsung Research Funding and Incubation Center of Samsung Electronics

National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT), Korea Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Reference29 articles.

1. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration

2. A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler

3. A 3.1 mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS;kull;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2013

4. A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS

5. A 1.4 mW 8b 350MS/s loop-unrolled SAR ADC with background offset calibration in 40 nm CMOS;ragab;Proc Eur Solid-State Circuits Conf (ESSCIRC),2016

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