Funder
National Key Research and Development Program of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
9 articles.
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1. CGAT- TICER: A Compressed GAT-based TICER for RC Reduction;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. P-TICER: An Effective Parallel TICER Acceleration Method for Model Order Reduction;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
3. TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order Reduction;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. CMOS substrate RC netlist reduction towards design cycle speed up;AEU - International Journal of Electronics and Communications;2023-11
5. Improve Sparse Implicit Projection Via Incomplete Cholesky Factorization;2023 China Semiconductor Technology International Conference (CSTIC);2023-06-26