Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process-Reference-Cited by-同舟云学术

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Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process

Published:2021-03 Issue:3 Volume:68 Page:1160-1170
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Wang Zhixuan¹^ORCID,Ye Le¹^ORCID,Huang Qianqian¹^ORCID,Du Kaixuan²,Tan Zhichao³,Wang Yangyuan¹,Huang Ru¹

Affiliation:

1. Key Laboratory of Microelectronics Devices and Circuits (MOE), Institute of Microelectronics, Peking University, Beijing, China

2. School of Electronics and Information Engineering, Anhui University, Hefei, China

3. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China

Funder

National Key Research and Development Program of China

National Science Foundation of China

Beijing New-star Plan of Science and Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9352589/09307262.pdf?arnumber=9307262

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