A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs
Author:
Affiliation:
1. Microelectronic Center, Harbin Institute of Technology, Harbin, China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9809931/09763878.pdf?arnumber=9763878
Reference41 articles.
1. Upset hardened memory design for submicron CMOS technology
2. Novel low cost, double- and-triple-node-upset-tolerant latch designs for nano-scale CMOS;yan;IEEE Trans Emerg Topics Comput,2018
3. Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop
4. Non-Volatile Spintronic Flip-Flop Design for Energy-Efficient SEU and DNU Resilience
5. Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs
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