An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin-Reference-Cited by-同舟云学术

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An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin

Published:1999 Issue:11 Volume:34 Page:1564-1570
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Cangsang Zhao ,Bhattacharya U.,Denham M.,Kolonsek J.,Lu Y.,Yong-Gee Ng ,Nintunze N.,Sarkez K.,Varadarajan H.D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/17376/00799864.pdf?arnumber=799864

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of 2-Stage Pipelining High-Performance SRAM;Advanced Materials Research;2012-12

2. Design and Experimental Validation of Radiation Hardened by Design SRAM Cells;IEEE Transactions on Nuclear Science;2010-02

3. A Digitally Controlled Oscillator for Low Jitter All Digital Phase Locked Loops;2005 IEEE Asian Solid-State Circuits Conference;2005-11

4. Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication;ETRI Journal;2005-02-11

5. A technology development SRAM approach with DFM considerations;2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072)

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