Affiliation:
1. Anhui University
2. School of Electronics and Information Engineering
Abstract
This paper describes a SRAM design using the pipelining technique which has been used in many microprocessors extensively. The main purpose to design SRAM with the technique of pipelining is to improve the whole performance of the SRAM based on the characteristic of the pipelining technique that it can incease exponentially the circuit performance. A 2-stage pipelining 4K SRAM has been verified by simulation, and the results demonstrate that the performance of the read operation can be improved twice if the pipelining technique has been used compared with the conventional SRAM operation.
Publisher
Trans Tech Publications, Ltd.
Reference12 articles.
1. Jeonghun, K., et al. : submitted to Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2011. 19(8): pp.1490-1495.
2. Liang, B.S., et al: submitted to VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on. (1997).
3. Mengxiao, L., et al. A Memory Access Scheduling Method for Multi-core Processor. in Computer Science and Engineering, 2009. WCSE '09. Second International Workshop on. (2009).
4. Sato, T. A simulation study of pipelining and decoupling a dynamic instruction scheduling mechanism. in EUROMICRO Conference, 1999. Proceedings. 25th. (1999).
5. Hashim, U. and M.N. Haron. Design of digital display system for ISFET pH sensor by using PIC microcontroller Unit (MCU). in Quality Electronic Design, 2009. ASQED 2009. 1st Asia Symposium on. (2009).
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献