Design space exploration of a software speculative parallelization scheme
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/71/30780/01425444.pdf?arnumber=1425444
Cited by 29 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. On the choice of the best chunk size for the speculative execution of loops;PLOS ONE;2022-05-17
2. Challenging Sequential Bitstream Processing via Principled Bitwise Speculation;Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems;2020-03-09
3. Validation of Context Preserving Thread-Level Speculative Execution Using N-Queens: Comparison of Non-CPSE and CPSE-enabled Applications;2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV);2017-12
4. Chunk-Wise Parallelization Based on Dynamic Performance Prediction on Heterogeneous Multicores;2017 International Conference on High Performance Computing & Simulation (HPCS);2017-07
5. A Survey on Thread-Level Speculation Techniques;ACM Computing Surveys;2016-11-11
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