Author:
Huh Jaehyuk,Kim Changkyu,Shafi Hazim,Zhang Lixin,Burger Doug,Keckler Stephen W.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Signal Processing
Cited by
42 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-09
2. Analyzing and Leveraging Shared L1 Caches in GPUs;Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques;2020-09-30
3. Rainbow: A composable coherence protocol for
multi‐chip
servers;Concurrency and Computation: Practice and Experience;2020-07-21
4. Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation;Journal of Systems Architecture;2019-11
5. A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism;Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019;2019