A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism-Reference-Cited by-同舟云学术

A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism

Published:2019 Issue: Volume: Page:
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Container-title:Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019
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Author:

Egawa Ryusuke¹,Saito Ryoma¹,Sato Masayuki¹,Kobayashi Hiroaki¹

Affiliation:

1. Tohoku University, Sendai, Miyagi, Japan

Publisher

ACM Press

Reference16 articles.

1. David H. Albonesi. 1999. Selective Cache Ways: On-Demand Cache Resource Allocation. In Proceedings of 32nd Annual International Symposium on Microarchitecture. 248--259.

2. T. E. Carlson, W. Heirman, and L. Eckhout. 2011. Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multicore Simulation. In Proceedings of International Conference for High Performance Computing, Networking, Storage and Analysis, Vol. 52.

3. Mainak Chaudhuri, Jayesh Gaur, Nithiyanandan Bashyam, Sreenivas Subramoney, and Joseph Nuzman. 2012. Introducing Hierarchy-awareness in Replacement and Bypass Algorithms for Last-level Caches. In Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques. 293--304.

4. Chiachen Chou, Aamer Jaleel, and Moinuddin K. Qureshi. 2015. BEAR: Techniques for Mitigating Bandwidth Bloat in Gigascale DRAM Caches. SIGARCH Comput. Archit. News 43, 3 (June 2015), 198--210.

5. et al. D. H. Bailey. 1991. The NAS Parallel Benchmarks. International Journal of High Performance Computing Applications 5, 3 (1991), 63--73.

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