Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications
Author:
Affiliation:
1. Indian Institute of Technology Roorkee,Department of Electronics and Communication Engineering,Roorkee,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9885796/9885734/09885891.pdf?arnumber=9885891
Reference15 articles.
1. Improving fMAX/fT ratio in FinFETs using source/drain extension region engineering
2. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size
3. A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs
4. Novel Physics-Based Small-Signal Modeling and Characterization for Advanced RF Bulk FinFETs
5. FinFET analogue characterization from DC to 110GHz
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