Reconfigurable CNN Accelerator Embedded in Instruction Extended RISC-V Core
Author:
Affiliation:
1. Tokyo Institute of Technology,Department Information and Communications Engineering,Tokyo,Japan
Funder
New Energy and Industrial Technology Development Organization
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10210847/10211258/10211513.pdf?arnumber=10211513
Reference16 articles.
1. The Speed Improvement by Merging Batch Normalization into Previously Linear Layer in CNN
2. A dynamic fixed-point representation for neuromorphic computing systems
3. Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators
4. Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
5. Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
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1. Energy-Efficient Implementation of YOLOv8, Instance Segmentation, and Pose Detection on RISC-V SoC;IEEE Access;2024
2. A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V;IPSJ Transactions on System and LSI Design Methodology;2024
3. Algorithm–Hardware Co-Optimization and Deployment Method for Field-Programmable Gate-Array-Based Convolutional Neural Network Remote Sensing Image Processing;Remote Sensing;2023-12-18
4. A Power-efficient end-to-end Implementation of YOLOv8 Based on RISC-V;2023 4th International Conference on Computers and Artificial Intelligence Technology (CAIT);2023-12-13
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