Hardware Optimization and FPGA Implementation of Pipelined ZUC Architecture-Reference-Cited by-同舟云学术

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Hardware Optimization and FPGA Implementation of Pipelined ZUC Architecture

Published:2021-12-17 Issue: Volume: Page:
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Container-title:2021 IEEE 6th International Conference on Computing, Communication and Automation (ICCCA)
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Author:

Hulle Nagnath,Prathiba B^ORCID,Khope Sarika R^ORCID

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9666052/9666199/09666269.pdf?arnumber=9666269

Reference32 articles.

1. XUPV5-LX110T;Xilinx com,2015

2. Combined and Robust SNOW-ZUC Algorithm Based on Chaotic System

3. Research and implementation of reconfigurable architecture of DES and ZUC

4. The Novel Architecture for Carry Lookahead Adder;hulle;Technical Journal of The Institution of Engineers (India) Pune Local Centre,2012

5. Comparison of the Hardware Implementation of Stream Ciphers;galanis;The International Arab Journal of Information Technology,2005

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. ZUC-256 High Throughput FPGA Implementation;2024 22nd International Conference on Optical Communications and Networks (ICOCN);2024-07-26

2. Satellite-Borne Fault-Tolerant Hardware Encryption for TT&C Data Secure Communication;2023 IEEE 23rd International Conference on Communication Technology (ICCT);2023-10-20

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