A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter-Reference-Cited by-同舟云学术

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A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter

Published:2022-07-17 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Conference on Real-time Computing and Robotics (RCAR)
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Author:

Xu Yue¹,Xie Jie¹,Xing Zhiwei²,Yuan Wenqiang¹,Yu Guanqun³,Zeng Zhongmin¹,Zhang Baoshun¹,Wu Dongmin¹

Affiliation:

1. Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences,Suzhou,China

2. Harbin Institute of Technology,Shenzhen,China

3. Shanghaitech University,School of Physical Science and Technology,Shanghai,China

Funder

Research and Development

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9872150/9872152/09872281.pdf?arnumber=9872281

Reference13 articles.

1. A multi-channel, 10ps resolution, FPGA-based TDC with 300MS/s throughput for open-source PET applications

2. A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays

3. A fast improved fat tree encoder for wave union TDC in an FPGA

4. Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Calibration Methods for Time-to-Digital Converters;Sensors;2023-03-03

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