Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond-Reference-Cited by-同舟云学术

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

Published:2022-12-03 Issue: Volume: Page:
ISSN:
Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Chang Chih-Hao¹,Chang V.S.¹,Pan K.H.¹,Lai K.T.¹,Lu J. H.¹,Ng J.A.¹,Chen C.Y.¹,Wu B.F.¹,Lin C.J.¹,Liang C.S.¹,Tsao C.P.¹,Mor Y.S.¹,Li C.T.¹,Lin T.C.¹,Hsieh C.H.¹,Chen P.N.¹,Hsu H.H.¹,Chen J.H.¹,Chen H.F.¹,Yeh J.Y.¹,Chiang M.C.¹,Lin C.Y.¹,Liaw J.J.¹,Wang C.H.¹,Lee S.B.¹,Chen C.C.¹,Lin H.J.¹,Chen R.¹,Chen K.W.¹,Chui C.O.¹,Yeo Y.C.¹,Huang K.B.¹,Lee T.L.¹,Tsai M.H.¹,Chen K.S.¹,Lu Y.C.¹,Jang S.M.¹,Wu S.-Y.¹

Affiliation:

1. Taiwan Semiconductor Manufacturing Company, Hsinchu,Taiwan,R.O.C

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019565.pdf?arnumber=10019565

Reference6 articles.

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