Network on Chip for 2D Mesh Toplological Structure in HDL Enviornment-Reference-Cited by-同舟云学术

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Network on Chip for 2D Mesh Toplological Structure in HDL Enviornment

Published:2023-12-01 Issue: Volume: Page:475-480
ISSN:
Container-title:2023 10th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)
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Author:

Kumar Santosh¹,Kumar Ashok²,Rana Vikrant³,Sharma Vibhoo⁴,Bhatnagar Vivek⁵,Sachi Savya⁶

Affiliation:

1. CSE-IOT Noida Institute of Engineering and Technology,Greater Noida

2. Koneru Lakshmaiah Education Foundation,Department of Computer Science & Engineering,Vaddeswaram, Guntur,AP,India

3. COER University,Department of Cyber Security,Roorkee

4. Hindustan College of Science and Technology,Department of IT,Mathura,D.P.,India

5. MMICT&BM(MCA) MM (Deemed to be University),Ambala,Haryana,India

6. Lalit Narayan Mishra College of Business Management,Department of Information Technology,Muzaffarpur,Bihar,India,842001

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10433942/10434287/10434451.pdf?arnumber=10434451

Reference11 articles.

1. Network on Chip for 3D Mesh Structure with Enhanced Security Algorithm in HDL Environment

2. Scalable Design and Synthesis of 3D Mesh Network on Chip

3. Task mapping and mesh topology exploration for an FPGA-based network on chip

4. Designing 2D and 3D Network-on-Chip Architectures

5. Applying partial power-gating to bit-sliced network-on-chip

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