An Investigation into the Impact of Using Automated Synthesisable Internal Power-Gating on Improved Power Efficiency for ASICs-Reference-Cited by-同舟云学术

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An Investigation into the Impact of Using Automated Synthesisable Internal Power-Gating on Improved Power Efficiency for ASICs

Published:2024-01-29 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 International Conference on Optimization Computing and Wireless Communication (ICOCWC)
language:
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Author:

Doda Davendra Kumar¹,Nidhya M.S.²,Acharjya Kalyan³

Affiliation:

1. Vivekananda Global University,Department of Electrical Engineering,Jaipur,India

2. Jain (Deemed to be University),Department of Computer Science and Information Technology,Bangalore,India

3. Maharishi School of Engineering & Technology, Maharishi University of Information Technology,Uttar Pradesh,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10470457/10470444/10470629.pdf?arnumber=10470629

Reference12 articles.

1. PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era

2. Dynamic power-gating for leakage power reduction in FPGAs

3. A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds

4. Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory

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