A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array
Author:
Affiliation:
1. National Tsing Hua University,Department of Electrical Engineering,Hsinchu,Taiwan
2. Taiwan Semiconductor Manufacturing Company, Ltd.,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9768045/9768046/09768060.pdf?arnumber=9768060
Reference18 articles.
1. Efficient built-in redundancy analysis for embedded memories with 2-D redundancy
2. On-chip Test and Repair of Memories for Static and Dynamic Faults
3. ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips
4. A shared parallel built-in self-repair scheme for random access memories in socs;tseng;2008 IEEE International Test Conference,2008
5. A Memory Built-In Self-Repair Scheme Based on Configurable Spares
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