Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits
Author:
Affiliation:
1. International Institute of Information Technology,Hyderabad
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9768045/9768046/09768067.pdf?arnumber=9768067
Reference16 articles.
1. Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence
2. Algorithm driven power-timing optimization method-ology for cmos digital circuits considering pvta variations;kalluru;2021 IEEE ISCAS,2021
3. Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models
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