Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Author:
Affiliation:
1. National Tsing Hua University,Dept. of Electrical Engineering,Hsinchu,Taiwan
2. Industrial Technology Research Institute,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9983856/9983857/09983882.pdf?arnumber=9983882
Reference19 articles.
1. Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective
2. Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN)
3. Neuron Fault Tolerance in Spiking Neural Networks
4. Spiking Neuron Hardware-Level Fault Modeling
5. Simulation-Based Test Algorithm Generation for Random Access Memories;wu;in Proc IEEE VLSI Test Symp (VTS),0
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1. Fault Analysis for a MTJ-based Spiking Neural Network;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09
2. Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
3. Characterization and Test of Intermittent Over RESET in RRAMs;2023 IEEE 32nd Asian Test Symposium (ATS);2023-10-14
4. Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
5. A Built-In Self-Calibration Scheme for Memristor-Based Spiking Neural Networks;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17
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