Fast Test Generation for Structurally Similar Circuits

Author:

Joe Jerin1,Mukherjee Nilanjan2,Pomeranz Irith1,Rajski Janusz2

Affiliation:

1. Purdue University,School of Electrical & Computer Engg.,W. Lafayette,IN,USA

2. Siemens Digital Industries Software,Wilsonville,OR,USA

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Generation of Two-Cycle Tests for Structurally Similar Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02

2. Testability Evaluation for Local Design Modifications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

3. Vector-deductive Memory-based Transactions for Fault-as-address Simulation;Èlektronnoe modelirovanie;2023-03-16

4. Vector-Deductive Memory-Based Transactions for Fault-As-Address Simulation;2022 12th International Conference on Dependable Systems, Services and Technologies (DESSERT);2022-12-09

5. Test Generation for an Iterative Design Flow with RTL Changes;2022 IEEE International Test Conference (ITC);2022-09

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