A survey of fault tolerance hardware architecture
Author:
Affiliation:
1. Purple Mountain Network Communications and Security Laboratory,Nanjing,China
2. Information Engineering University,Zhengzhou,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10013311/10013093/10013336.pdf?arnumber=10013336
Reference11 articles.
1. Design of SoC for High Reliability Systems with Embedded Processors;yiu;Embedded World Conference,0
2. Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V
3. Schreiber, Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC for High Consequence Applications;kral;Sand,2017
4. Novel lockstep-based fault mitigation approach for SoCs with roll-back and roll-forward recovery
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1. Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects;Lecture Notes in Electrical Engineering;2024
2. Homogeneous Tightly-Coupled Dual Core Lock-Step with No Checkpointing Redundancy;Lecture Notes in Electrical Engineering;2023-11-29
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