TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis-Reference-Cited by-同舟云学术

TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis

Published:2017-04 Issue:4 Volume:36 Page:655-668
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Sengupta Anirban^ORCID,Bhadauria Saumya,Mohanty Saraju P.

Funder

Science and Engineering Research Board, Department of Science and Technology, Government of India

Department of Science and Technology (Science and Engineering Research Board), Government of India

Intel Corporation

Department of Electronics and IT, Government of India

National Science Foundation

Semiconductor Research Corporation

Air Force

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

Cited by 48 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

3. Security of Hardware Generators: Enabling Assurance in High-Level Synthesis;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

5. SecHLS;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16