A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators-Reference-Cited by-同舟云学术

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A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators

Published:2018-02 Issue:2 Volume:37 Page:420-430
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Ayupov Andrey,Yesil Serif,Ozdal Muhammet Mustafa^ORCID,Kim Taemin,Burns Steven,Ozturk Ozcan

Funder

European Union H2020-MSCA-IF Program

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/8263325/07932131.pdf?arnumber=7932131

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Flip : Data-centric Edge CGRA Accelerator;ACM Transactions on Design Automation of Electronic Systems;2023-12-18

2. SCV-GNN: Sparse Compressed Vector-Based Graph Neural Network Aggregation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12

3. Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

4. Non-relational Databases on FPGAs: Survey, Design Decisions, Challenges;ACM Computing Surveys;2023-02-09

5. HLS-based High-throughput and Work-efficient Synthesizable Graph Processing Template Pipeline;ACM Transactions on Embedded Computing Systems;2023-01-24

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