Author:
Chung Jaeyong,Xiong Jinjun,Zolotov Vladimir,Abraham Jacob A.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
5 articles.
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2. A Hierarchical Technique for Statistical Path Selection and Criticality Computation;ACM Transactions on Design Automation of Electronic Systems;2017-10-17
3. Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-09
4. Statistical Criticality Computation Using the Circuit Delay;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-05
5. On Computing Criticality in Refactored Timing Graphs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2012-12