A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures-Reference-Cited by-同舟云学术

A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures

Published:2016-03 Issue:3 Volume:35 Page:471-484
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Qian Zhi-Liang,Juan Da-Cheng,Bogdan Paul,Tsui Chi-Ying,Marculescu Diana,Marculescu Radu

Funder

Hong Kong Research Grants Council

HKUST Sponsorship Scheme for Targeted Strategic Partnerships

U.S. National Science Foundation (NSF)

NSF

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/7419205/07229288.pdf?arnumber=7229288

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