Polyhedral Compilation for Racetrack Memories

Author:

Khan Asif AliORCID,Mewes Hauke,Grosser TobiasORCID,Hoefler Torsten,Castrillon JeronimoORCID

Funder

German Research Council (DFG) through the TraceSymm Project

Cluster of Excellence “Center for Advancing Electronics Dresden;”

Swiss National Science Foundation under the Ambizione Program

ARM Holdings plc and Xilinx Inc.

Polly Labs

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories;IEEE Transactions on Computers;2023-09-01

2. Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT;IEEE Transactions on Computers;2023-04-01

3. Pinning Fault Mode Modeling for DWM Shifting;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-07

4. Fast-track cache;Proceedings of the 36th ACM International Conference on Supercomputing;2022-06-28

5. MemUnison: A Racetrack-ReRAM-combined Pipeline Architecture for Energy-Efficient in-Memory CNNs;IEEE Transactions on Computers;2022

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