Fast-track cache-Reference-Cited by-同舟云学术

Fast-track cache

Published:2022-06-28 Issue: Volume: Page:
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Container-title:Proceedings of the 36th ACM International Conference on Supercomputing
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Author:

Tárrega Hugo¹,Valero Alejandro²,Lorente Vicente¹,Petit Salvador¹,Sahuquillo Julio¹

Affiliation:

1. Universitat Politècnica de València, Valencia, Spain

2. Universidad de Zaragoza, Zaragoza, Spain

Funder

Ministerio de Ciencia, Innovación y Universidades and the European ERDF

Dept. of Science, University, and Knowledge Society, Government of Aragon

Agencia Estatal de Investigación (AEI)

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3524059.3532383

Reference49 articles.

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2. S. Archer , G. Mappouras , R. Calderbank , and D. J. Sorin . 2020. Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory . In Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. 331--342 . S. Archer, G. Mappouras, R. Calderbank, and D. J. Sorin. 2020. Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory. In Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. 331--342.

3. Reducing shift penalty in Domain Wall Memory through register locality

4. E. Atoofian and A. Saghir . 2015. Shift-Aware Racetrack Memory . In Proceedings of the 33rd IEEE International Conference on Computer Design. 427--430 . E. Atoofian and A. Saghir. 2015. Shift-Aware Racetrack Memory. In Proceedings of the 33rd IEEE International Conference on Computer Design. 427--430.

5. Coding for Racetrack Memories