MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks

Author:

Sie Syuan-Hao,Lee Jye-Luen,Chen Yi-Ren,Yeh Zuo-wei,Li Zhaofang,Lu Chih-Cheng,Hsieh Chih-Cheng,Chang Meng-Fan,Tang Kea-Tiong

Funder

Ministry of Science and Technology Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. SUN: Dynamic Hybrid-Precision SRAM-Based CIM Accelerator With High Macro Utilization Using Structured Pruning Mixed-Precision Networks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-07

3. CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Tool;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05

4. A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05

5. A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC;Microelectronics Journal;2024-03

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