Author:
Kuo-Hsing Cheng ,Chih-Sheng Huang
Cited by
5 articles.
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1. Analysis of 6T Full Adder using 2T XOR and 2T XNOR Module;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08
2. High‐speed and area‐efficient scalable
N
‐bit digital comparator;IET Circuits, Devices & Systems;2020-03-10
3. Energy-efficient single-clock-cycle binary comparator;International Journal of Circuit Theory and Applications;2010-07-25
4. A new low-power high-speed single-clock-cycle binary comparator;Proceedings of 2010 IEEE International Symposium on Circuits and Systems;2010-05
5. Design methodologies for high-performance noise-tolerant XOR-XNOR circuits;IEEE Transactions on Circuits and Systems I: Regular Papers;2006-04